Variable input-impedance circuit arrangement



FIG.2

INVENTOR.

FIG.4

. J. ENSINK Original Filed July 20, 1956 VARIABLE INPUT-IMPEDANCE CIRCUIT ARRANGEMENT FIGJ Aug. 27, 1963 JOHANNES ENSINK PIC-3.5

wawhaum (PPEC 39 w United States Patent Office 3,102,215 Patented Aug. 27, 1963 3,102,215 VARIABLE INPUT-IMPEDAN CE CIRCUIT ARRANGEMENT Johannes Ensink, Hilvers'um, Netherlands, assignor, by

mesne assignments, to North American Philips Company, Inc., New York, N.Y., a corporation of Delaware Original application July 20, 1956, Ser. No. 599,163, now Patent No; 2,952,783, dated Sept. 13, 1960. Divided and this application Apr. 12, 1960, Ser. No. 48,795

2 Claims. (Cl. 317-1485) This invention relates to transistor circuit-arrangements comprising a variable input impedance in order to influence the amplitude of an electrical oscillation. it is known to vary the input impedance of a transistor by varying" the emitter adjustment current to which this input impedance is inversely proportional to a first approximation.

This application is a division of application Serial No. 599,163, filed July 20, 1956, now Patent No. 2,952,783, granted September 13, 1960. e

The present invention utilises the variation occurring in the input impedance if the oscillation produced at the collector causes the collector voltage to drop temporarily substantially to the emitter voltage (collector limitation). In accordance with the present invention, the emitter and base electrodes of the transistor with an emitter-collector current amplification factor substantially unity are coupled to'a source of oscillations. The internal resistance of the source of oscillations, viewed between these electrodes, lies between the values of the input impedance of the transistor, measured with a collector impedance zero and infinity, respectively. The electrical oscillation is supplied to said electrodes with an amplitude sufiicient to make the collector-emitter. voltage substantially zero during the maxima of said oscillation the resultant varying input impedance of the transistor producing a variable damping of the source of oscillations.

The invention may be used with particular advantage in two related classes of circuit arrangements. In the first class, the invention has the feature that the transistor with an emitter-collector current-amplification factor approXi-' mately unity is operated in common base arrangement and its emitter and base are coupled to a series-resonance circuit, the resonance resistance of which viewed between these electrodes, lies between the values of the input impedance of the transistor, measured with a collector impedance zero and infinity respectively. The electrical oscillation is supplied to said resonant circuit with an amplitude sufiicient to make the collector-emitter voltage substantially zero and to cause the resultant varying input impedance of the transistor to damp the resonant circuit more heavily during the maxima of said oscillation. In the second class, the invention has the feature that the transistor with an emitter-collector amplification factor substantially unity is operated in common emitter arrangement and its emitter and base are coupled to a parallel-resonance circuit, the resonance resistance of which, viewed between these electrodes, lies bet-ween the. values of the input impedance of the transistor measured with a collector impedance zero and infinite respectively. The electrical oscillation is supplied to this resonance circuit with an amplitude sufiicient to make the collectoremitter voltage substantially zero and to cause the resultant varying input impedance of the transistor to damp the resonant circuit more heavily during the maxima of said oscillation.

In order that the invention may be readily carried into effect it will now be described with reference to the accompanying drawing, in which FIG. 1 is a schematic diagram of an embodiment of the circuit arrangement of the present invention;

FIG. 2 is an equivalent diagram of FIG. 1;

FIG. 3 is a schematic diagram of another embodiment of the circuit arrangement of the present invention;

FIG. 4 is a schematic diagram of anembodiment based on that of FIG. 3; and

FIG. 5 is a schematic diagram of an embodiment based on that of FIG. 4.

FIG. 1 shows a transistor 1 in common base arrangement, that is to say that the base is common to the input and output circuit. Connected between the emitter and the base is a series-resonance circuit comprising a capacitor 2 and an inductance 3-, the latter being coupled to a signal current source 4 which corresponds to the reso- 'nance frequency of the circuit 2-3. The collector circuit furthermore comprises a parallel resonance circuit 5 tuned to the signal frequency.

'In the equivalent diagram shown in FIG. 2, the transistor 1 isreplaced in known manner by its internal resistance parameters r r r and the source of current on z' where oz represents the collector-emitter current amplification factor which is approximately equal to unity and i represents the emitter current. Furthermore, the circuit 2, 3, comprises a resonance resistance 6 (in which the attenuation by the generator 4 has been accounted for) and the circuit 5 comprises a resonance resistance 7.

According to a partial feature of the invention the resistance 6 has a value inbetween the values of the input resistance of the transistor at the values of the resistance 7=zero and infinity respectively. The values r +r (l-a) and r +r are calculated respectively for the input resistance. The invention is based on the recognition that if the signal oscillations are supplied to the cirlcuit 2, 3-with such a high amplitude and amplified in the transistor that the collector-emitter voltage becomes substantially zero during the maxima of said oscillations, the collector resistor r of the transistor then changes abruptly from a considerable value (for example several megohms), and more particularly high relatively to the resistance 7, to a very low value (for example several tens of ohms) and more particularly low relatively to the resistance 7, so that in fact the aforesaid condition is satisfied, the input impedance varying from the'value r +r (l-a) to r +r Since an is substantially unity, this variation entails a considerable increase in damping of the circuit 2, 3, hence the oscillation across'this circuit assumes a considerably smaller amplitude.

If, for example, the source 4 supplies an amplitudemodulated current of sufficient strength, the current passing through the transistor 1 and the voltage set up across the circuit 5 will substantially exhibit no further amplitude modulation. If desired, the signal oscillation of the source 4 may be made. sufiicient to urge the emitter periodically in the blocking direction relative to the base, which also involves a considerable increase in input impedance.

In FIG. 3, the transistor 10 is operated in common emitter arrangement, inwhich are coupled to a partial winding 11 of a parallel-resonance circuit 12, to which the oscillation from the source 4 is supplied. For the input impedance of the transistor a value varies according to the aforesaid expressions and the.

the emitter and the base,

circuit. 12 is damped more heavily. In this case, however, the driving of thebase of thetransistor 10 in the blocking direction reduces the damping.

vIn FIG. 4, the circuit arrangement shownvin FIG. 3 is extendedto form a modulation circuit arrangement, in

which the source 4f supplies a carrier oscillation to the transistor 10, while a modulating oscillation from a source, 15 produces via atransistor 16 \acorresponding amplified voltage'across a common collector impedance 17 which,v J

by collector limitation, limits the carrier voltage produced across the circuit 5 to a value corresponding to the modulating oscillation, so that the input impedance of the transistor 10 andconsequently the oscillation acrossthe circuit 12 also vary in accordance with said modulating.

oscillation.

In FIG. 5', this principle is use d inla circuit arrange:

ment for frequency-telegraphy reception. The incoming telegraph signals from the source 20 are supplied toa network 21 which is selective both in regard to the carrier frequency and the operating frequency of said signals and w-hidhsuppliesthe oscillations of these frequencies to the base-emitter circuits of two transistors 23 and 24-respectively, the. output'currents of which, after detection, pass through, a differential relay 25. The detection circuits comprise two transistors 26 and 27 respectively, the bases, of which are connected to the emitters of the transistors 23 andc24. respectively, while their through-connected emitters are maintained at a low'blocking potential by means, of .potentiometers 28 and; 29 respectively. the, amplitude of the oscillations-suppliedto the; transistors 23v and 24' respectively exceeds said blocking potential; a corresponding current is supplied t,o.the relay by thetransi stors 26 and 27 respectively. TIlhe-voltage dropproduced bysaid current across the resistor 29;in-

- l olves an increase of the blocking potential produced, thus. improving the trigger-sensitivity of the circuit arrange. ,m n

Across common collector resistorsj30 and31 of the.

ti'ansistors123 and-24 respectivelyoscillations of a suffi periodically and damp the selective network 21 more,

heavilyr; "llhisyields anincrease in insensitivity ;with re-. spect to voice noise, since if the-frequency of thissignal oscillator issuch that forexample, the oscillation supplied to the transistorlfi, exceeds that supplied to the transistor ing of the resonance .circuitoccurs uponcollector limitaq tion, for example by substitutingin FIG. 1 a'parallel-circuit for the resonance circuit 2, 3 or by substituting a series-circuit for the parallel circuit 12 in FIG. 3. If,

furthermore, the circuit capacitor 2 is completely omitted V in FIG. 1, the voltage produced between the emitter and, the base upon collector limitation will abruptly increase I with the voltage of the source 4 much more rapidly than in the absence of collector limitation, which effect may be employed for impulse triggers in television circuit arrangements.

What is claimed is: I i l. A circuitar-rangement comprising first andjsecond transistors each having emitter, collector and base electrodes-and an emitter-collector current amplification factor a substantially equal to unity, a source of electrical oscillationsQaresOnant selective network having an internal in-' put resistance viewed from the emitter and base electrodes of 'saidfirst and second transistors'of a value between the values'of the input impedance of said first. and second transistors when the collector impedance of said first and second transistors is zero and-when said collector impedance-is' substantially infinity, said selective network being interposed-between said source of oscillations and the baseelectrodes of said first and second transistors, said selective network comprising two portions each tuned to a different frequency, one portion being coupledto the base of said first transistor, the second portionbeing coupled to the base of said second transisto'r, said source of oscillations containing frequencies to which said selective network is tuned,'and an impedance coupled incommon in the collector electrode circuits of said first and second transistors, said first and second oscillations having an amplitude producing a substantially z'ero collectoremitter voltage simultaneously in said first and second transistors when the amplitude of said first and second 2. A circuit arrangement comprising first and second transistors each having emitter, collector and'base electrodes and an emitter-collector current amplification factor substantially equal to unity, a source of electrical oscilsecond transistors when the collector impedance of said first andsecond transistors is zero and when said collector said selective network comprising two portions each tuned to a different frequency, one portion bein'g coupled to the base of said first transistor, the second portion being coupled to the base of said second transistor, said source of oscillations containing frequencies to which said selec- .tive network is tuned, an impedance coupled in common 24, then, ,upon theoccurrence of said'noise, when both the in the collector electrode circuits of said first and second transistors, said first and secondoscillations having an amplitude producing a substantially zero collector-emitter voltage simultaneously in said firstand second transistors when the amplitude of said first and second oscillations is Y a'm'aximum whereby said input impedance of said first and second transistors varies to provide selective variable dampingofboth portions of said selective network, said damping beinga maximum when said oscillation ampli tude is a maximum and the initial magnitude ratio of said first and second oscillations is maintained, differential relay means, and detecting means interposed between said "first and second transistors and said relay means, said detecting means comprising third and fourth transistors each baring emitter, collector and base electrodes,

7 with the base electrode of said fourth transistor, means connecting the emitter electrodes of said third and'fourth transistors to each other and means connecting the collector electrodes of said third and fonrth transistors to said relay means. I 7

References Cited in the file of this patent UNITED STATES PATENTS Pinckaers Sept. 24', 1957 Pinckaers Mar. 25, 1958 V Linvill et a1. Apr. 15, 1958 Bright Nov. 29, '1960 

1. A CIRCUIT ARRANGEMENT COMPRISING FIRST AND SECOND TRANSISTORS EACH HAVING EMITTER, COLLECTOR AND BASE ELECTRODES AND AN EMITTER-COLLECTOR CURRENT AMPLIFICATION FACTOR SUBSTANTIALLY EQUAL TO UNITY, A SOURCE OF ELECTRICAL OSCILLATIONS, A RESONANT SELECTIVE NETWORK HAVING AN INTERNAL INPUT RESISTANCE VIEWED FROM THE EMITTER AND BASE ELECTRODES OF SAID FIRST AND SECOND TRANSISTORS OF A VALUE BETWEEN THE VALUES OF THE INPUT IMPEDANCE OF SAID FIRST AND SECOND TRANSISTORS WHEN THE COLLECTOR IMPEDANCE OF SAID FIRST AND SECOND TRANSISTORS IS ZERO AND WHEN SAID COLLECTOR IMPEDANCE IS SUBSTANTIALLY INFINITY, SAID SELECTIVE NETWORK BEING INTERPOSED BETWEEN SAID SOURCE OF OSCILLATIONS AND THE BASE ELECTRODES OF SAID FIRST AND SECOND TRANSISTORS, SAID SELECTIVE NETWORK COMPRISING TWO PORTION BEING COUPLED TO THE A DIFFERENT FREQUENCY, ONE PORTION BEING COUPLED TO THE BASE OF SAID FIRST TRANSISTOR, THE SECOND PORTION BEING COUPLED TO THE BASE OF SAID SECOND TRANSISTOR, SAID SOURCE OF OSCILLATIONS CONTAINING FREQUENCIES TO WHICH SAID SELECTIVE NETWORK IS TUNED, AND AN IMPEDANCE COUPLED IN COMMON IN THE COLLECTOR ELECTRODE CIRCUITS OF SAID FIRST AND SECOND TRANSISTORS, SAID FIRST AND SECOND OSCILLATIONS HAVING AN AMPLITUDE PRODUCING A SUBSTANTIALLY ZERO COLLECTOREMITTER VOLTAGE SIMULTANEOUSLY IN SAID FIRST AND SECOND TRANSISTORS WHEN THE AMPLITUDE OF SAID FIRST AND SECOND OSCILLATIONS IS A MAXIMUM WHEREBY SAID INPUT IMPEDANCE OF SAID FIRST AND SECOND TRANSISTORS VARIES TO PROVIDE SELECTIVE VARIABLE DAMPING OF BOTH PORTIONS OF SAID SELECTIVE NETWORK, SAID DAMPING BEING A MAXIMUM WHEN SAID OSCILLATION AMPLITUDE IS A MAXIMUM AND THE INITIAL MAGNITUDE RATIO OF SAID FIRST AND SECOND OSCILLATIONS IS MAINTAINED. 